ECE · Digital Design and VLSI
Digital Electronics and VLSI Design Fundamentals Internship
Move from digital logic to a simulated RTL design, verification plan and synthesis review.
A digital design internship that connects Boolean logic, sequential systems, HDL modeling, testbenches and introductory synthesis concepts.
Program overview
Eligible branches: Electronics and Communication Engineering, Electrical and Electronics Engineering, Electronics and Instrumentation, Computer Engineering
Target learner level: Learners who know basic digital logic and want a guided introduction to RTL design and verification.
Prerequisites: Basic algebra and interest in digital circuits · No prior chip fabrication experience required
Technologies and tools
Boolean algebra · combinational and sequential logic · finite-state machines · Verilog/SystemVerilog · testbenches · waveform inspection · synthesis reports
Practical assignments
- Design a combinational block from a written specification
- Implement and simulate a finite-state machine
- Write a testbench and inspect synthesis timing or area reports
Capstone project
Specify, implement, verify and review a digital subsystem through a simulation and synthesis workflow.
Expected deliverables
- RTL source and design specification
- Testbench, simulation logs and waveforms
- Synthesis report with trade-off notes
- Verification checklist
- Design review presentation
Learning outcomes
- Analyze combinational and sequential digital circuits
- Model and verify an RTL block using an HDL
- Interpret basic synthesis and timing reports
Week-by-week curriculum
The program follows a 13-week core pathway. Weeks 14–15 are optional advanced work when the project scope calls for it.
Weeks 1–2
Orientation, fundamentals and setup
- Orientation, EDA workflow, number systems and digital design setup
- Boolean algebra, logic gates, K-maps and combinational circuit analysis
Weeks 3–5
Core concepts and guided learning
- Adders, comparators, multiplexers and finite-state-machine design
- Flip-flops, counters, timing concepts and synchronous design discipline
- Verilog/SystemVerilog modules, testbenches and waveform inspection
Weeks 6–8
Intermediate concepts and practical exercises
- RTL coding style, parameterization and reusable design blocks
- Assertions, directed/random test cases and functional coverage concepts
- Synthesis flow, constraints, area reports and critical-path interpretation
Weeks 9–11
Advanced topics, specialist tools and project development
- Clock-domain crossing awareness, reset strategy and timing closure basics
- Design-for-test concepts, power/area/performance trade-offs and linting
- Develop an RTL capstone with specification, verification and synthesis goals
Weeks 12–13
Capstone completion, testing, documentation and evaluation
- Implement and verify the selected digital subsystem
- Run simulation, lint and synthesis; resolve functional/timing issues
- Submit RTL, testbench, waveforms, design notes and evaluation presentation
Weeks 14–15 · Optional
Advanced extension and final presentation
- Add a protocol feature or optimize area/timing within constraints
- Expand test coverage and present a revised synthesis comparison
Frequently asked questions
Is prior experience required?
The prerequisites listed on this page describe helpful preparation. The opening weeks include a guided refresher; learners should be ready to practise consistently and complete project work.
Does this include fabrication or a silicon tape-out?
No. This is a fundamentals and simulation-focused learning program; semiconductor fabrication or tape-out is not included.